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IRDC3629
USER GUIDE FOR IR3629 EVALUATION BOARD (Vin=12V, Vo=1.8V, Io=20A)
DESCRIPTION
The IR3629 is a synchronous buck controller, providing a compact, high performance and flexible solution in a small 3mmx4mm MLPD package. Key features offered by the IR3629 include programmable soft-start ramp, precision 0.6V reference voltage, thermal protection, fixed 600kHz switching frequency requiring no external component, input under-voltage lockout for proper start-up, and pre-bias startup. An output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance. This user guide contains the schematic and bill of materials for the IR3629 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for the IR3629 integrated circuit is available in the IR3629 data sheet.
BOARD FEATURES * Vin = +12V (13.2V Max) * Vout = +1.8V @ 0-20A * IRF6712 as Controller MOSFET * IRF6715 as Synchronous MOSFET * L = 0.36uH * Cin=33uF (SP cap) + 2x10uF (ceramic 1206) * Cout=6x22uF(ceramic 1206) * Optional external supply connection for Vc * Optional Power-good output connection
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IRDC3629
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 A maximum of 20A load can be
IR3629 demo board can also be powered by two separate power supplies, one is the input voltage (Vin) between VIN+ and VIN-, the other is bias voltage (Vcc) between Vc-ext and PGND. In this case, a well regulated 5V~12V power supply should be connected to Vc-ext and PGND and R14 should be removed. Inputs and outputs of the board are listed in Table I. Table I. Connections
Connection VIN+ VINVc-ext PGND VOUTVOUT+ GND Signal Name Vin (+12V) Ground of Vin Optional Vcc input Ground for optional Vcc input Ground of Vout Vout (+1.8V) Bias Voltage Ground
LAYOUT
The PCB is a 6-layer board. All of layers are 2 Oz. copper. Power supply decoupling capacitors, the chargepump capacitor and feedback components are located close to the IR3629. The feedback resistors are connected to the output voltage at the point of regulation and are located close to the IC. The input and output energy storage capacitors and the power inductor are located on bottom side of the board, to improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path.
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IRDC3629
IR3629 Demo Board
Vin= 12V
Vo=1.8V
Fig. 1 Connection diagram of the evaluation board for IR3629 (Top view)
Fig. 2 Bottom view of the evaluation board for IR3629
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IRDC3629
IR3629 PCB Layers
Top Layer
Bottom Layer
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IRDC3629
IR3629 PCB Layers
PGND
AGND
Mid-layer1
Single point connection between PGND and AGND
Mid-layer2
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IRDC3629
IR3629 PCB Layers
Mid-layer3
Mid-layer4
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IRDC3629
IR3629 Demo Board Schematic
PGND 1 Vc-ext 1 Vin 1
Vin+
R14 33 C4 0.1uF R15 N/A C3 10uF C2 10uF C1 33uF + 1
1
Vin+
D1 BAT54S 2 PGND C22 1 1uF En PGood Vout 1 R7 31.6K R17 4.99K 2 1 C23 0.1uF 11 10 1 7 C10 0.1uF R5 13.3K R1 13.3K C11 39pF 1 9 C26 1.8nF 8 U1 Vcc SS/SD GND PGood Vsens Comp Fb Vc HDrv OCSet LDrv PGND Thermal 6
3
1
Vin-
1 C25 0.1uF 1 2 6 7 VinC12 0.1uF
Q1 5 N3064730 C24 1 2 3 6 4 7 12 3 4 13 R12 2.94K C9 N/A 1 VoutNo Stuff N3065372 5 3 4 Q2 IRF6715 MX 5 IRF6712 SQ SW 1 N30652001 0.36uH L1 2 C15 22uF C16 22uF C17 22uF C18 22uF C19 22uF C20 22uF 1 C14 0.1uF 1 Vout 1 Vout+
IR3629
Vout+
Vout-
AGND
R10 No Stuff
R9 0 R4 1.96K C8 180pF R2 60.4K R3 30.1K 1 R6 20 1
A
B
R* 0
Fig. 3 Schematic of the IR3629 evaluation board with 12Vin and1.8V output voltage
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IRDC3629
BILL OF MATERIALS
Item 1 2 Quantity 1 2 Reference C1 C2,C3 C4,C10,C12 C14,C23, C25 C8 C11 C15,C16, C17,C18, C19,C20 C22 C26 D1 L1 Q1 Q2 R9 R1 R2 R7 R3 R4 R5 R6 R12 R17 Value 33uF 10uF Description POSCAP, 25V, 20% Ceramic, 25V, X7R, 10% Ceramic, 25V, X7R, 10% Ceramic, 50V, C0G, 5% Ceramic, 50V, C0G, 5% Ceramic, 6.3V, X5R, 20% Ceramic, 16V, X5R, 10% Ceramic, 50V, C0G, 5% Dual Schottky Diode 1.1mOhm NFET, 25V, 3.8mOhm, 12nC NFET, 25V, 1.3mOhm, 40nC Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Thick film, 1%, 1/10W Size 1206 Manufacturer Sanyo Murata Part Number 25TQC33M GRM31CR61C106KA88
3 4 5
6 1 1
0.1uF 180pF 39pF
603 603 603
TDK Murata Murata
C1608X7R1H104K GRM1885C1H181JA01D GRM1885C1H390JA01D
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22uF 1uF 1.8nF BAT54S 0.36uH IRF6712 SQ IRF6715 MX 0 13.3K 60.4K 31.6K 30.1K 1.96K 13.3K 20 2.94K 4.99K
1206 603 603 SOT-23 DirectFET SQ DirectFET MX 603 603 603 603 603 603 603 603 603 603
Panasonic TDK Murata Vishay Panasonic IR IR any any any any any any any any any any
ECJDV50J226M C1608X5R1C105K GRM1885C1H182JA01D BAT54S ETQP4LR36WFC IRF6712SPbF IRF6715MPbF any any any any any any any any any any
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IRDC3629
BILL OF MATERIALS (cont.)
Item 23 24 25 26 27 Quantity 1 1 2 1 2 Reference R14 U1 C9, C24 C21 R10,R15 Value 33 IR3629 No Stuff No Stuff No Stuff Banana Jack, Insulated, Solder Terminal, Black Banana Jack, Insulated, Solder Terminal, Red Banana Jack, Insulated, Solder Terminal, Green Description Thick film, 1%, 1/4W PWM Controller Size 1206 MLPD 3x4 603 603 Johnson Components Johnson Components Johnson Components Manufacturer any IR Part Number any IR3629MPbF
28
2
-
-
-
105-0853-001
29
1
-
-
-
105-0852-001
30
1
-
-
-
105-0854-001
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IRDC3629
TRACKING OPERATING PERFORMANCE Vin=12.0V, Vo=1.8V, Fs=600kHz, Room Temperature, No Air Flow
Fig. 4 Start Up at 20A Ch1:Vin, Ch2:Vss, Ch3:PGood, Ch4:Vout
Fig. 5 Prebias Start Up Ch1:Vin, Ch2:Vss, Ch4:Vout
Fig. 6 Output Voltage Ripple at 20A Load Ch1:Vout, Ch3:SW
Fig. 7 Gate Signals at 20A Load Ch1:LDRV, Ch2:HDRV, Ch3:SW
Fig. 8 Transient Response Ch1:Vout, Ch2:Io(0-10A)
Fig. 9 Shorted Hiccup Condition Recovery Ch2:Vout, Ch3:Vss, Ch4:Io
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IRDC3629
TYPICAL OPERATING PERFORMANCE Vin=12.0V, Vo=1.8V, Io=0-20A, Fs=600kHz, Air Flow=200LFM
Fig. 10 Bode Plot of Control Loop
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IRDC3629
TYPICAL OPERATING PERFORMANCE Vin=12.0V, Vo=1.8V, Fs=600kHz, Room Temp, No Air Flow
IR3629 Efficiency
100 90 Efficiency(%) 80 70 60 50
0.0
2.5
5.0
7.5
10.0
12.5
15.0
Iout(A)
Fig. 11 Efficiency vs. Load
2
1
Fig. 12 Thermal Image of IR3629 Demo Board at Io=15A (1: IR3629, 2: IRF6715, 3: IRF6712)
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IRDC3629
PCB Metal and Components Placement
The lead land width should be equal to the nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. The lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. The center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be 0.17mm for 2 oz. Copper ( 0.1mm for 1 oz. Copper and 0.23mm for 3 oz. Copper). Two 0.30mm diameter via should be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC.
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IRDC3629
Solder Resist
The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist misalignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. The land pad should be Non Solder Mask Defined (NSMD), with a minimum pullback of the solder resist off the copper of 0.06mm to accommodate solder resist mis-alignment. Ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Each via in the land pad should be tented or plugged from bottom boardside with solder resist.
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IRDC3629
Stencil Design
The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. The land pad aperture should deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
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IRDC3629
IR3629 MLPD Package 3x4-12Lead
E/2 E
S Y M B O L A A1 A3 b D2 D E E2 L e N ND
D
VGED-4
MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.02 0.05 0.20 REF 0.18 0.25 0.30 3.70 _ 4.00 BSC 3.00 BSC 1.40 _ 1.80 0.30 0.40 0.50 0.50 PITCH 12 6 3.0 INCHES NOM MAX .035 .039 .0008 .0019 .008 REF .0118 .0071 .0096 MIN .032 .000 _ .145 .157 BSC .118 BSC .055 _ .070 .016 .012 .019 .020 PITCH 10 6 .118
A A1 D2
A3
SEATING PLANE
E2
Terminal 1 Identifier
Leads on 2 sides
b (ND-1) x e e L
TAPE & REEL ORIENTATION
Figure A
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01
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